VLSI and its Impact on Nanotechnology

INTRODUCTION

This blog presents an in depth study of this VLSI technological aspects, importance and their replacement or combination with the Nanotechnology within the VLSI world of silicon semiconductors. Various technologies have been brought in nanotechnology in silicon world which aims to shrink geometry of CMOS devices to Nano scale. This also refers to a replacement world of nanotechnology where chemists are working in manufacturing of carbon nanotubes , Nano devices of varies materials of Nano dimensions without even knowing how this might change the entire world of Si and CMOS technology and therefore the world we sleep in. 

The VLSI technology means 10s of millions of CMOS transistors in microns on a silicon wafer of a few cm dimensions. The Moore's law continues to hold good with the continuous advances in the VLSI technology and design issues. Also different materials are replacing the conventional silicon wafers and aluminum metal interconnects to achieve more density per chip to cope up with the miniaturization in the technology and it is believed that their might be a dead end to the CMOS technology in future if we try to keep on going with this trend. Silicon wafers have been replaced with the Silicon-on-Insulator and low k-dielectric cost of chip masks and next-generation fabrication plants totally replacing todays foundries. In spite of advances this industry and research, a threat to economic issues holds as the continuing scaling of Silicon transistors brings about a new, exciting era of nanoscale technology to silicon foundries.

Nanotechnology and CAEN


CAEN which is Chemically assembled electronic Nanotechnology is a form of electronic nanotechnology(EN). It mainly uses self alignment to construct electronic circuits out of Nanometer scale devices. CAEN devices can replace CMOS-based devices in near future. A full spectrum of integrated circuit products down to 90-nm technology node are being manufactured. Well known companies like IBM and INTEL have also launched a few chips using 65 nm technologies like Quad core processor




Nano wires and Interconnects

Stochastically assembled nanoscale architectures have the potential to achieve device densities 100 times greater than today's CMOS. The main challenge which is faced in nanotechnologies is controlling parallel sets of nanowires(NWs), such as those in crossbars using a moderate number mesoscale wires.
There are basically 3-methods to this:
  • NW differentiation during manufacture
  • Random connections between NWs and mesoscale wires
  • Mask-based approach
Each of these addressing schemes involves a stochastic step in their implementation.

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